Transistor Characteristics

Transistor Characteristics and Parameters

The ratio of the dc collector current (IC) to the dc base current (IB) is the dc beta (bDC).

bDC is called the gain of a transistor:

bDC = IC/IB

Typical values of bDC range from less than 20 to 200 or higher.

bDC is usually designated as an equivalent hybrid (h) parameter:

hFE = bDC

The ratio of the collector current (IC) to the dc emitter current (IE) is the dc alpha (aDC). This is a less-used parameter than beta.

aDC = IC/IE

Typical values range from 0.95 to 0.99 or greater.

aDC is always less than 1.

This is because IC is always slightly less than IE by the amount of IB.

From graph above we can see that there are 6 important parameters to be considered:

i) IB: dc base current.

ii) IE: dc emitter current.

iii) IC: dc collector current.

iv) VBE: dc voltage at base with respect to emitter.

v) VCB: dc voltage at collector with respect to base.

vi) VCE: dc voltage at collector with respect to emitter.

VBB forward-biases the BE junction.

VCC reverse-biases the BC junction.

When the BE junction is forward biased, it is like a forward biased diode:

VBE ? 0.7 V

But it can be as high as 0.9 V (and is dependent on current). We will use 0.7 V from now on.

Emitter is at ground. Thus the voltage across RB is

VR(B) = VBB- VBE

Also

VR(B) = I­RRB

Or:

RRB = VBB- VBE

Solving:

IB = (VBB- VBE)/RB

Voltage at collector with respect to grounded emitter is:

VCE = VCC – VR(C)

Since drop across RC is VR(C) = ICRC the voltage at the collector is also:

VCE = VCC - ICRC

Where IC = bDCIB. Voltage across the reverse-biased collector-bias junction is

VCB = VCE - VBE

Example:

Determine IB, IC, IE, VBE, VCE, and VCB in the following circuit. The transistor has bDC 150.

Solution:

We know VBE=0.7 V. Using the already known equations:

IB = (VBB- VBE)/RB

IB = (5 – 0.7)/10kW = 430 mA

IC = bDCIB = (150)( 430 mA) = 64.5 mA

IE = IC + IB = 64.5 mA + 430 mA = 64.9 mA

Solving for VCE and VCB:

VCE = VCC – ICRC = 10V-(64.5mA)(100W) = 3.55 V

VCB = VCE – VBE = 3.55 V – 0.7 V­ = 2.85 V

Since the collector is at higher potential than the base, the collector-base junction is reverse-biased.

Changing the voltage supplies with variable voltage supplies in the circuit above, we can get the characteristic curves of the BJT.

If we start at some positive VBB and VCC = 0 V, the BE junction and the BC junction are forward biased.

In this case the base current is through the BE junction because of the low impedance path to ground, thus IC is zero.

When both junctions are forward-biased, the transistor is in the saturation region of operation.

As VCC is increase, VCE gradually increases, as the I­C increases (This is the steep slope linear region before the small-slope region).

IC increases as VCC ­increase because VCE remains less than 0.7 V due to the forward-biased base-collector junction.

Ideally, when VCE exceeds 0.7 V, the BC junction becomes reverse biased.

Then, the transistor goes into the linear region of operation.

When the BC junction is reverse-biased, IC levels off and remains essentially constant for a given value of IB as VCE continues to increase.

Actually, there is a slight increase in IC, due to the widening of the BC collector depletion region, which results in fewer holes for recombination in the base, which causes a slight increase in bDC.

For the linear portion, the value of I­C is calculated by:

IC = bDCB

When VCE reaches a sufficiently large voltage, the reverse biased BC junction goes into breakdown.

Thus, the collector current increases rapidly.

A transistor should never be operated in this region.

When IB = 0, the transistor is in the cutoff region, although there is a small collector leakage current.

i) Cutoff

As said before, when IB = 0, transistor is in cutoff region.

There is a small collector leakage current, I­CEO.

Normally it is neglected so that VCE = VCC.

In cutoff, both the base-emitter and the base-collector junctions are reverse-biased.

ii) Saturation

When BE junction becomes forward biased and the base current is increased, IC also increase (I­CbDCIB) and VCE decreases as a result of more drop across the collector resistor (VCE = VCC – ICRC).

When VCE reaches its saturation value, VCE(sat), the BC junction becomes forward-biased and I­C can increase no further even with a continued increase in IB.

At the point of saturation, IC = bDCIB is no longer valid.

VCE(sat) for a transistor occurs somewhere below the knee of the collector curves.

It is usually only a few tenths of a volt for silicon transistors.

iii) DC load line

Cutoff and saturation can be illustrated by the use of a load line.

Bottom of load line is at ideal cutoff (IC = 0 and VCE = VCC).

Top of load line is at saturation (IC = IC(sat) and VCE = VCE(sat))

In between cutoff and saturation along the load line is the active region.

More to come later.

Example

Determine whether or not the transistor in circuit below is in saturation. Assume VCE(sat) = 0.2 V.

First determine IC(sat).

IC(sat) = (VCC – VCE(sat))/RC

IC(sat) =(10 V – 0.2V)/10kW = 9.8 mA

Now let’s determine whether IB is large enough to produce IC(sat).

IB = (VBB - VBE)/RB = (3 V – 0.7 V)/10kW = 0.23 mA

IC = bDCIB = (50)(0.23 mA) = 11.5 mA

This shows that with the specified bDC, this base current is capable of producing an IC greater than IC(sat). Thus, the transistor is saturated, and the collector current value of 11.5 mA is never reached. If you further increase I­B, the collector current remains at its saturation value.

i) More on bDC

The bDC of hFE is not truly constant.

It varies with collector current and with temperature.

Keeping the junction temperature constant and increasing IC causes bDC to increase to a maximum.

Further increase in IC beyond this point causes bDC to decrease.

If IC is held constant and temperature varies, bDC changes directly with temperature.

Transistor data specify bDC at specific values. Normally the bDC specified is the maximum value.

ii) Maximum transistor ratings

Maximum ratings are given for collector-to-base voltage, collector-to-emitter voltage, emitter-to-base voltage, collector current, and power dissipation.

The product VCEIC must not exceed PD(max).

Example:

The transistor shown in the figure below has the following maximum ratings: PD(max)=800 mW, VCE(max) = 15 V, and IC(max) = 100 mA. Determine the maximum value to which VCC can be adjusted without exceeding a rating. Which rating would be exceeded first?

Solution:

First, find IB, so that you can determine IC.

I­B = (VBB – VBE)/RB = (5 V – 0.7 V)/22 kW = 195 mA

IC = bDCIB = (100)(195 mA) = 19.5 mA

IC is much less than IC(max) and will not change with VCC. It is determined only by IB and bDC.

The voltage drop across RC is

R(C) =ICRC = (19.5 mA)(1 kW) = 19.5 V

Now we can determine the value of VCC when VCE = VCE(max) = 15 V.

VR(C) = VCC - VCE

So,

VCC(max) = VCE(max) + VR(C) = 15 V + 19.5V = 34.5 V

VCC can be increased to 34.5 V, under the existing conditions, before VCE(max) is exceeded. However, at this point it is not known whether or not PD(max) has been exceeded:

PD = VCE(max)IC = (15 V)(19.5 mA) = 293 mW

Since PD(max) is 800 mW, it is not exceeded when VCC = 34.5 V. So, VCE(max) = 15 V is the limiting rating in this case. If the base current is removed, causing the transistor to turn off, VCE(max) will be exceeded first because the entire supply voltage, VCC, will be dropped across the transistor.

Op-Amps with negative feedback

There are several basic ways in which an op-amp can be connected using negative feedback to stabilize the gain and increase frequency response.

The large open-loop gain of an op-amp creates instability because a small noise voltage on the input can be amplified to a point where the amplifier is driven out of the linear region.

Open-loop gain varies between devices.

Closed-loop gain is independent of the open-loop gain.

Closed-Loop voltage gain, Acl

It is the voltage gain of an op-amp with external feedback.

Gain is controlled by external components.

Noninverting Amplifier

The op-amp circuit shown below is a non-inverting amplifier in a closed-loop configuration.

Input signal is applied to the non-inverting input.

The output is applied back to the inverting input through feedback (closed loop) circuit formed by the input resistor Ri and the feedback resistor Rf.

This creates a negative feedback.

The two resistors create a voltage divider, which reduces Vout and connects the reduced voltage Vf to the inverting input.

The feedback voltage is:

Vf = Ri/(Ri + Rf)Vout

The difference between the input voltage and the feedback voltage is the differential input to the op-amp.

This differential voltage is amplified by the open loop gain, Aol, to get Vout­.

Vout­ = Aol(Vin – Vf)

Let B = Ri/(Ri + Rf). Thus Vf = BVout and

Vout = Aol(Vin – BVout)

Manipulate the expression to get:

Vout = AolVin - AolBVout

Vout + AolBVout = AolVin

Vout(1 + AolB) = AolVin

Overall Gain = Vout/Vin = Aol/(1 + AolB)

Since AolB >> 1, the equation above becomes:

Vout/Vin = Aol/(AolB) = 1/B

Thus the closed loop gain of the noninverting (NI) amplifier is the reciprocal of the attenuation (B) of the feedback circuit (voltage-divider).

Acl(NI) = Vout/Vin = 1/B = (Ri + Rf)/Ri

Finally:

Acl(NI) = 1 + Rf/Ri

Notice that the closed loop gain is independent of the open-loop gain.

Example

Determine the gain of the amplifier circuit shown below. The open loop gain of the op-amp is 150000.

Solution

This is a noninverting amplifier op-amp configuration. Therefore, the closed-loop voltage gain is

Acl(NI) = 1 + Rf/Ri = 1 + 100 k?/4.7 k? = 22.3

Voltage-Follower (VF)

Output voltage of a noninverting amplifier is fed back to the inverting input by a straight connection.

The straight feedback has a gain of 1 (i.e. there is no gain).

The closed-loop voltage gain is 1/B, but B = 1. Thus, the Acl(VF) = 1.

It has very high input impedance and low output impedance.

Inverting Amplifier (I)

The input signal is applied through a series input resistor Ri to the inverting input.

The output is fed back through Rf to the same input.

The noninverting input is grounded.

For finding the gain, let’s assume there is infinite impedance at the input (i.e. between the inverting and non-inverting inputs).

Infinite input impedance implies zero current at the inverting input.

If there is zero current through the input impedance, there is NO voltage drop between the inverting and noninverting inputs.

Thus, the voltage at the inverting input is zero!

- The zero at the inverting input is referred to as virtual ground.

Since there is no current at the inverting input, the current through Ri and the current through Rf are equal:

Iin = If.

The voltage across Ri equals Vin because of virtual ground on the other side of the resistor. Therefore we have that

Iin = Vin/Ri.

Also, the voltage across Rf equals –Vout, because of virtual ground. Therefore:

If = -Vout/Rf

Since If = Iin, we get that:

-Vout/Rf = Vin/Ri

Or, rearranging,

Vout/Vin = -Rf/Ri

So,

Acl(I) = -Rf/Ri

Thus, the closed loop gain is independent of the op-amp’s internal open-loop gain.

The negative feedback stabilizes the voltage gain.

The negative sign indicates inversion.

Diode limiting and clamping circuits

a) Limiters:

Diodes can be used to clip off portions of signal voltages (above or below certain levels).

Diode will become forward biased as soon as VA becomes larger than VBIAS+0.7.

When diode is forward biased, VA cannot become larger than VBIAS + 0.7 V!

Thus, the voltage across the load, RL, will also be equal to VBIAS + 0.7.

When diode is reverse biased, it appears as an open, so the output voltage is the voltage of RL alone.

Desired voltage levels can be attained with a voltage divider.

We replace the voltage source with a resistive voltage divider.

VBIAS = R3/(R2 + R3) VSUPPLY

Example:

b) Diode Clampers

A clamper adds a dc level to an ac voltage.

Also called dc restorers.

When input voltage goes initially negative, diode is forward biased.

Capacitor charges to near peak of inpt (Vp(in) – 0.7).

Right after the negative peak, diode is reverse biased (because cathode is held near Vp(in) – 0.7 by charge on capacitor).

Capacitor can only discharge through the RL.

Since RL has high resistance, the capacitor discharges very little each period.

Note that time constant should be large (at least 10 times the period of the input voltage).

Since capacitor retains charge, it acts like a battery in series with the input voltage.

L

Robust Engineering "Innovative Product design Ideas"













Plastic Egg Cartons "-: Reusable "crack free eggs" cartons


If we look at the market places, we would be able to find products like this already from
Fall Harvest
Products™ Plastic cartons.

But this product is disposable and is a vacuum formed blistering plastic product.

We think we can design better product than this existing product design, through improved design ideas.

1. We are aiming to reuse these plastic egg trays so that it would be an environmental friendly plastic product.

2. We are aiming to use clear engineering plastics and latest mould design techniques so that we can utilize our design skills to redesign differently and focus to protect the eggs from being damaged. (During loading, unloading and its transport)

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Plastic Mould design Principles 1. Mould cooling


A competent mould designer must have a through knowledge of the Engineering principles behind the mould designs.

First of all we will try to cover the Mould cooling


One fundamental principle of Plastic Injection moulding is that hot material enters the mould, where it cools rapidly to a temperature at which it solidifies sufficiently to retain the shape of the part. The temperature of the mould is therefore very important as it governs a portion of the overall moulding cycle. Also ttemperature control of moulds directly proposal to the properties of the thermoplastic injection moulded parts as well.
While the melt flows more freely in a hot mould, a greater cooling period is required before the solidified moulding can be ejected. Again if the melt solidifies too quickly in a cold mould it may not be able to reach the extremities of the cavity. So therefore a compromise between the two extremes must be accepted to obtain the optimum moulding cycle.
Today most of the people are willing to do their Plastic mould design/Manufacture in China. The reason behind this decision was the term "cheep" in other words when they do they can save huge money in $$$. Now I will show you what could be the dangers would come behind this cheep tooling process and what could be the subsequent long term problems will arise and would effect the quality of the Injection moulded plastic part and eventually the final risk involved to collapse the whole engineering systems.

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